1. Field of the Technology
The present technology relates to high density memory devices, and particularly the operation of devices using stacked memory structures.
2. Description of Related Art
As critical dimensions of devices in integrated circuits shrink toward perceived limits of manufacturing technologies, designers have been looking to techniques to achieve greater storage capacity, and to achieve lower costs per bit. Technologies being pursued include multiple layers of memory cells on a single chip. Operations performed on a 3D (three-dimensional) NAND memory having multiple layers of memory cells include read, write and erase.
Typically, erase operations are performed by blocks of memory cells, where the general issue of high density NAND, and in particular high density 3D NAND, memories is that the size of a block of memory cells is often very large. This is not convenient if a user only needs to change the code of a small unit stored in a 3D NAND memory. As the density of 3D NAND memories increases, the number of layers in the stacks increase, leading to larger block sizes and further inconvenience in erase operations.
Thus, it is desirable to provide for a technology with more efficient and convenient erase operations in 3D NAND memories.